 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Features * * * * * * * * Fully integrated TX/RX with VCO Fast Settling Synthesizer Unlimited Multi-slot Operation with Advanced Closed-loop Modulation No Mechanical Tuning Required Low Current Consumption Auxiliary Voltage Regulator On-chip (3.2 V to 4.6 V) Supply-voltage Range 3 V to 4.6 V (Regulated) Ramp-signal Generator for Power Ramping and Power Control of External SiGe Power Amplifier (T7024) * Supports Multiple Reference Clocks (10.368 MHz/ 13.824 MHz/ 20.736 MHz/ 27.648 MHz) * TX Preamplifier with 3 dBm Output Power at 2.45 GHz * Few Low-cost External Components Description The T2802 is an RF IC for low-power applications in the 2.45 GHz ISM band. The HP-VFQFP-N48-packaged IC is a complete transceiver including image rejection mixer, IF amplifier, FM demodulator, baseband filter, RSSI, TX preamplifier, powerramping generator for power amplifiers, integrated synthesizer, fully integrated VCO, TX filter and modulation compensation circuit for advanced closed-loop modulation concept. No mechanical tuning is necessary in production. 2.5 GHz WDECT/ISM Single-chip Transceiver T2802 Preliminary Figure 1. Block Diagram MIXER IF_IN OUT IR MIXER RF_IN DEMOD BB FILTER RAMP_OUT RAMP_SET RAMP GEN RAMP D/A D/A RSSI DEMOD DAC RSSI GF TX_DATA DEMOD IF_TANK IF AMP 1 IF AMP 2 BB_OUT TANK CF VCO TX / RX SWITCH PC TX_OUT f :n TX DRIVER PD MCC 3-WIRE BUS CLOCK DATA ENABLE PU_VCO VCO REG AUX REG CP RC f :n CTRL LOGIC RX_ON TX_ON PU_RX/TX PU_PLL VREG_VCO VS_VCO VREG VS_REG VTUNE GND_VCO PU_REG REG_CTRL CP I_CPSW LD REF_CLK Rev. 4509A-DECT-01/02 1 Table 1. Functional Block Description Name AUX REG BBF CP DAC DEMOD GF IF AMP1 IF AMP2 IR MIXER MCC PC PD RAMP GEN RC RSSI TX DRIVER TX/RX SWITCH VCO VCO REG Description Auxiliary voltage regulator Baseband filter Charge pump D/A converter for demodulator tuning Demodulator Gaussian filter for transmit data 1st intermediate frequency amplifier 2nd intermediate frequency amplifier Image rejection mixer Modulation compensation circuit Programmable counter Phase detector Ramp-signal generator Reference counter Received signal-strength indicator Buffer amplifier for TX_OUT Switches VCO signal to IR MIXER resp. TX DRIVER Voltage-controlled oscillator Voltage regulator for VCO Pin Configuration Figure 2. Pinning HP-VFQFP-N48 MIXER_OUT2 MIXER_OUT1 TX_DATA PU_VCO VS_MIXER PU_RX/TX GND_PLL PU_PLL RX_ON TX_ON RAMP_SET I_CPSW 48 CLOCK DATA ENABLE REF_CLK LD PU_REG VS_PLL VREG REG_CTRL VS_REG GND_CP VS_CP 1 2 3 4 5 6 7 8 9 10 11 12 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 RAMP_OUT IF_IN2 IF_IN1 VS_IF TX_OUT GND3 RF_IN2 RF_IN1 GND2 IF_TANK2 IF_TANK1 RSSI T2802 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 GND_VCO VREG_VCO GND1 CP DEMOD_TANK1 DEMOD_TANK2 DAC_DEC REG_DEC VTUNE 2 T2802 4509A-DECT-01/02 VS_VCO BB_OUT BB_CF T2802 Pin Description Pin Symbol Function VS_PLL Configuration 7 1 CLOCK 3-wire-bus: Clock input 2 DATA 3-wire-bus: Data input CLOCK DATA ENABLE 1,2,3 5k 5k 3 ENABLE 3-wire-bus: Enable input GND_PLL VS_PLL 7 4 REF_CLK Reference-frequency input REF_CLK 10k 10k 4 GND_PLL 43 LD 5 100 5 LD Lock-detect output GND_PLL 43 PU_REG 6 6 PU_REG Power-up input for auxiliary voltage regulator GND_PLL 43 25k 25k 3 4509A-DECT-01/02 Pin Description Pin Symbol Function VS_PLL Configuration 7 VS_REG 10 VS_CP 12 VS_VCO 14 GND1 18 GND2 28 GND3 31 7 VS_PLL PLL supply voltage VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 VS_REG 10 REG_CTRL 9 8 VREG Auxiliary voltage-regulator output VREG 8 9 REG_CTRL Auxiliary voltage-regulator control output 10 VS_REG Auxiliary voltage-regulator supply voltage GND_PLL 43 VS_CP 12 11 12 13 GND_CP VS_CP CP Charge-pump ground Charge-pump supply voltage Charge-pump output GND_CP 11 CP 13 4 T2802 4509A-DECT-01/02 T2802 Pin Description Pin Symbol Function Configuration VS_VCO 14 14 15 16 VS_VCO VREG_VCO GND_VCO VCO voltage-regulator supply voltage VCO voltage-regulator control output VCO ground VREG_VCO 15 GND_VCO 16 VREG_VCO 15 17 VTUNE VCO tuning voltage input VTUNE 17 GND_VCO 16 VS_PLL 7 VS_REG 10 VS_CP 12 VS_VCO 14 GND1 18 GND2 28 GND3 31 18 GND1 Ground VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 5 4509A-DECT-01/02 Pin Description Pin Symbol Function Configuration VS_MIXER 42 10k 10k 19 DEMOD_TANK1 Demodulator tank circuit DEMOD DEMOD TANK1 19 TANK2 20 20 DEMOD_TANK2 Demodulator tank circuit GND1 18 VREG_VCO 15 10k DAC_DEC 21 21 DAC_DEC Decoupling PIN for VCO_DAC 400 GND_VCO 16 VREG_VCO 15 2k 22 REG_DEC Decoupling PIN for VCO_REG REG_DEC 22 42k GND_VCO 16 VS_IF 33 23 BB_CF Baseband filter corner-frequency control input BB_CF 23 GND1 18 6 T2802 4509A-DECT-01/02 T2802 Pin Description Pin Symbol Function VS_IF 33 Configuration 24 BB_OUT Baseband filter output BB_OUT 24 GND1 18 VS_IF 33 25 RSSI Received signal strength indicator output 13k RSSI 25 GND2 28 VS_IF 33 IF TANK1 26 5k 5k IF TANK2 27 26 IF_TANK1 IF tank circuit 27 IF_TANK2 IF tank circuit GND2 28 VS_PLL 7 VS_REG 10 VS_CP 12 VS_VCO 14 GND1 18 GND2 28 GND3 31 28 GND2 Ground VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 7 4509A-DECT-01/02 Pin Description Pin Symbol Function VS_MIXER 42 Configuration 29 RF_IN1 RF input of image reject mixer RF_IN1 29 RF_IN2 30 30 RF_IN2 RF input of image reject mixer GND2 28 VS_PLL 7 VS_REG 10 VS_CP 12 VS_VCO 14 GND1 18 GND2 28 GND3 31 31 GND3 Ground VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 TX_OUT 32 GND_PLL 43 32 TX_OUT TX driver amplifier output for PA GND3 31 8 T2802 4509A-DECT-01/02 T2802 Pin Description Pin Symbol Function VS_PLL Configuration 7 VS_REG 10 VS_CP 12 VS_VCO 14 GND1 18 GND2 28 GND3 31 33 VS_IF IF amplifier supply voltage VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 VS_IF 33 34 IF_IN1 IF input of IF amplifier IF_IN1 34 4.3k IF_IN2 35 35 IF_IN2 IF input of IF amplifier GND2 28 VS_MIXER 42 36 RAMP_OUT Ramp-generator output for PA power ramping RAMP_OUT 36 GND2 28 9 4509A-DECT-01/02 Pin Description Pin Symbol Function Configuration VS MIXER 42 RAMP 37 RAMP_SET Slew-rate setting of ramping signal 1k 100 SET 37 GND2 25 VS_IF 33 38 RX_ON RX control input RX_ON TX_ON 38, 39 5k 5k 39 TX_ON TX control input GND1 18 VS_MIXER 42 40 MIXER_OUT1 Mixer output to SAW filter MIXER_ OUT1 40 270 270 MIXER_ OUT2 41 41 MIXER_OUT2 Mixer output to SAW filter GND2 28 10 T2802 4509A-DECT-01/02 T2802 Pin Description Pin Symbol Function VS_PLL Configuration 7 VS_REG 10 VS_CP 12 GND1 18 GND2 28 42 VS_MIXER Mixer supply voltage VS_VCO 14 GND3 31 43 GND_PLL PLL ground VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 VS_VCO 14 GND_PLL 43 44 PU_VCO VCO power-up input PU_VCO 44 5k 5k GND_VCO 16 PU_RX/TX 45 45 PU_RX/TX RX/TX power-up input GND18 18 25k 25k 11 4509A-DECT-01/02 Pin Description Pin Symbol Function Configuration 20k 10k 140k 46 PU_PLL PLL power-up input PU PLL 46 25k 25k GND PLL 43 VS_PLL 7 47 TX_DATA TX data input of Gaussian filter and modulationcompensation circuit TX_DATA 47 5k GND_PLL 43 VS_PLL 7 48 I_CPSW Charge-pump current control input I_CPSW 48 5k GND_PLL 43 12 T2802 4509A-DECT-01/02 T2802 Functional Description Receiver The RF signal at RF_IN is fed to an image rejection mixer IR_MIXER with its differential outputs MIXER_OUT1 and MIXER_OUT2 driving an IF-SAW filter at 110.592 MHz or 112.32 MHz. The IF amplifiers IF_AMP1 and IF_AMP2 with an external IF_TANK and an integrated RSSI function feed the signal to the demodulator DEMOD working at f = f IF /2 (55 MHz) and finally to an integrated baseband filter BB. For demodulator tunning in production an integrated 5-bit digital-to-analog (D/A) converter is provided to control the on-chip varicap diode. The transmit data at TX_DATA is filtered by an integrated Gaussian Filter GF and fed to the fully integrated VCO operating at twice the output frequency. After modulation the signal is frequency-divided by 2 and fed via a TX/RX SWITCH to the TX_DRIVER. This bus-controlled driver amplifier supplies typically +3 dBm output power at TX_OUT. A ramp-signal generator RAMP_GEN, providing a ramp signal at RAMP_OUT for the external power amplifier, is integrated. The slope of the ramp signal is controlled by a capacitor at the RAMP_SET pin. The IR_MIXER, the TX_DRIVER and the programmable counter PC are driven by the fully integrated VCO (including on-chip inductors and varactors). A 3-bit digital-to-analog converter is used to pretune the frequency. The output signal is frequency-divided to supply the desired frequency to the TX_DRIVER, 0/90 degree phase shifter for the IR_MIXER and to be used by the PC for the phase detector PD (fPD = 3.456 MHz). Unlimited multislot operation is possible by using the integrated advanced closed-loop modulation concept based on the modulation compensation circuit MCC. An integrated bandgap-stabilized voltage regulator for use with an external low-cost PNP transistor is implemented. Multiple power-down and current saving modes are provided. Transmitter Synthesizer Power Supply 13 4509A-DECT-01/02 Figure 3. PLL Principle RF_IN Programable counter PC "- Main counter MC "- Swallow counter SC fVCO = fPD x (SMC x 32 + SSC) fVCO ext. loop filter Phase frequency detector PD fPD = 3.456 MHz PA driver Charge pump VCO Divider by 2 Mixer VCO DAC GF_DATA Controlled phase shifting Modulation compensation MCC Gaussian filter GF Reference counter RC REF_CLK 10.368 MHz 13.824 MHz 20.736 MHz 27.648 MHz SRC 3 4 6 8 6.912 MHz 1.152 Mbit/s PLL reference Frequency REF_CLK Baseband controller TX_DATA 14 T2802 4509A-DECT-01/02 T2802 The following table shows the LO frequencies for RX and TX for the DECT band plus additional channels for the extended DECT band. Intermediate frequencies of 110.592 MHz and 112.32 MHz are supported. Table 1. LO Frequencies Mode TX TX TX TX TX RX RX RX RX RX RX RX RX RX RX 112.320 (for 13.824 MHz/ 27.648 MHz REF_CLK recommended) 110.592 (for 10.368 MHz/ 20.736 MHz REF_CLK recommended) fIF/MHz Channel C0 C1 ... C45 C46 C0 C1 ... C45 C46 C0 C1 ... C45 C46 fANT/MHz 2401.920 2403.648 ... 2479.680 2481.408 2401.920 2403.648 ... 2479.680 2481.408 2401.920 2403.648 ... 2479.680 2481.408 fVCO/MHz 2401.920 2403.648 ... 2479.680 2498.688 2291.328 2293.056 ... 2369.088 2370.816 2289.600 2291.328 ... 2367.360 2369.088 SMC 43 43 ... 44 44 41 41 ... 42 42 41 41 ... 42 42 SSC 14 15 ... 27 28 14 15 ... 27 28 13 14 ... 26 27 Formula TX: fANT = fVCO = 1.728 MHz x (32 x SMC + SSC) RX: fANT = 1.728 MHz x (32 x SMC + SSC) + fIF Control Signals Table 2. Control Signals -- Functions Signal I_CPSW PU_REG PU_VCO PU_RX/TX PU_PLL RX_ON TX_ON Data Word 1 Bit D10 Data Word 1 Bit D9 Functions Charge pump current control Activates AUX voltage regulator supplying the complete transceiver Activates VCO voltage regulator which supplies only the VCO Activates RX/TX switch Activates PLL circuits: PC, PD, CP, RC Activates RX circuits: BBF, DEMOD, IF AMP, IR MIXER Activates TX circuits: TX-DRIVER, RAMP GEN. Starts RAMP SIGNAL at RAMP OUT Activates GF in TX mode Activates MCC in TX mode 15 4509A-DECT-01/02 Table 3. Control Signals -- Modes Modes PU_REG PU_VCO PU_RX/TX PU_PLL RX_ON TX_ON BB filter Demodulator IF amplifiers and RSSI IR mixer RX switch TX switch TX driver Ramp generator Programmable counter Voltage-controlled oscillator Gaussian filter Phase detector / charge pump Modulation compensation circuit Reference counter Typ. current consumption / mA @ VS = 3.2 V TX Mode 1 1 1 1 0 1 OFF OFF OFF OFF OFF ON ON ON ON ON ON ON ON ON TBD RX Mode 1 1 1 1 1 0 ON ON ON ON ON OFF OFF OFF ON ON OFF ON OFF ON TBD RSSI Only 1 1 1 1 1 1 OFF OFF ON ON ON OFF OFF OFF ON ON OFF ON OFF ON TBD Serial Programming Bus The transceiver is programmed by the 3-wire bus (CLOCK, DATA and ENABLE). After the setting enable signal to low condition on the rising edge of the clock signal, the data is transferred bit by bit into the shift register, starting with the MSB-bit. When the enable signal has returned to high condition, the programmed information is loaded into the addressed latches according to the address bit condition (last bit). Additional leading bits are ignored and there is no check made how many pulses arrived during enable low condition. During enable low condition the bus current is increased to speed up the bus logic. To keep all information in the registers during standby, DATA_HOLD must be set to high condition. In this case the power-down current is below 100 A. The programming of the transceiver is separated into two data words. Data word 1 controls mainly the channel information together with settings, which are closely related with the channel. Dataword 2 holds setup information, which is adjusted during production. 16 T2802 4509A-DECT-01/02 T2802 Data Word 1 MSB Data bits LSB Address bit D21 RC D20 D19 D18 SC D17 D16 D15 D14 MC D13 D12 VS D11 X D10 MCC D9 D8 GFCS D7 D6 D5 D4 D3 D2 D1 D0 GF A0 D22 VCODAC CPCS D11 = x: do not care Data Word 2 E12 PA E11 E10 E9 E8 E7 E6 E5 E4 MCCS E3 E2 E1 TEST E0 A0 0 DEMODDAC/RAMPDAC Data Word 1 Programs PLL Settings With the Reference Counter bits D21 - D22 RC (Reference Counter) D22 0 0 1 1 D21 0 1 0 1 SRC 3 4 6 8 REF_CLK 10.368 MHz 13.824 MHz 20.736 MHz 27.648 MHz With the Main Counter bits D13 - D15 MC (Main Counter) D15 0 0 ... 1 1 D14 0 0 ... 1 1 D13 0 1 ... 0 1 SMS 40 41 ... 46 47 With the Swallow Counter bits D16 - D20 SC (Swallow Counter) D20 0 0 0 ... 1 1 1 D19 0 0 0 ... 1 1 1 D18 0 0 0 ... 1 1 1 D17 0 0 1 ... 0 1 1 D16 0 1 0 ... 1 0 1 SSC 0 1 2 ... 29 30 31 17 4509A-DECT-01/02 VCO Selection With bit D12 VCO Selection D12 0 1 VCO Mode RX-VCO TX-VCO Gaussian Filter on/off With bit D0 GF is used only in TX mode D0 0 1 GF (Gaussian Filter) OFF ON Modulation Compensation Circuit on/off With bit D10 MCC is used only in TX mode D10 0 1 MCC (Modulation Compensation Circuit) OFF ON GFCS Adjustment With bits D7 - D9 Only in TX mode effective for setting the frequency deviation of the modulation GFCS (Gaussian Filter Settings) D9 0 0 0 0 1 1 1 1 D8 0 0 1 1 0 0 1 1 D7 0 1 0 1 0 1 0 1 GFCS 60% 70% 80% 90% 100% 110% 120% 130% VCO_DAC Adjustment With bits D3 - D6 Used to pretune the VCO frequency in case of production tolerances of the device. Tuning voltage in locked condition should be around 1.8 V at room temperature. This gives margin for ambient temperature changes. Pretune DAC Voltage D6 0 0 0 ... 1 1 1 D5 0 0 0 ... 1 1 1 D4 0 0 1 ... 0 1 1 D3 0 1 0 ... 1 0 1 fVCO/% -5 ... ... ... ... ... 5 18 T2802 4509A-DECT-01/02 T2802 CPCS Adjustment With bits D1 - D2 Used to adjust the charge pump current. This can be used to compensate the change of the tuning sensitivity over frequency and device tolerances. CPCS (Charge-Pump Current Settings) D2 0 0 1 1 D1 0 1 0 1 CPCS -1 0 1 2 Data Word 2 Programs DEMODDAC Adjustment With bits E6 - E10 Only in RX mode effective. Used to tune the demodulator center frequency and allows to compensate tolerances of external components and the T2802. Demod DAC Voltage E10 0 0 0 ... 1 1 1 E9 0 0 0 ... 1 1 1 E8 0 0 0 ... 1 1 1 E7 0 0 1 ... 0 1 1 E6 0 1 0 ... 1 0 1 fIFcenter % -5 ... ... ... ... ... 5 RAMPDAC Adjustment for TX Mode With bits E6 - E10 Only in TX mode effective. Used to control the power of the external PA by adjusting the ramping voltage. RAMPDAC Voltage (@ Pin 36 RAMP_OUT) E10 0 0 0 ... 1 1 ... 1 1 E9 0 0 0 ... 0 1 ... 1 1 E8 0 0 0 ... 1 0 ... 1 1 E7 0 0 1 ... 1 0 ... 1 1 E6 0 1 0 ... 1 0 ... 0 1 VRAMP_OUT 1.1 V ... ... ... 1.68 V 1.7 V ... ... 1.7 V 19 4509A-DECT-01/02 MCCS Adjustment With bits E3 - E5 Only in TX mode effective. Adjusts the modulation compensation circuit for closed-loop modulation. This adjustment is done with a test sequence of a long stream of ,1` - ,0`. The correct setting is achieved if the modulation is not affected by the PLL. MCCS (Modulation Compensation Settings) E5 0 0 0 0 1 1 1 1 E4 0 0 1 1 0 0 1 1 E3 0 1 0 1 0 1 0 1 MCCS 60% 70% 80% 90% 100% 110% 120% 130% TEST Mode Settings With bits E0 - E2 In normal operation Lock detect output is used. All other settings are for test only. E2 0 0 0 0 1 1 1 1 E1 0 0 1 1 0 0 1 1 E0 0 1 0 1 0 1 0 1 Signal at Lock Detect Output Lock detect PC out RC out MCCTEST: RC out divided by 2048 Lock detect PC out RC out GFTEST: RC out divided by 2 CP Mode Active Active Active Active High imp. High imp. High imp. High imp. Output Power Settings With bits E11 - E12 PA (Output Power Settings) E12 0 0 1 1 E11 0 1 0 1 PA -21 dBm -11 dBm -4 dBm +3 dBm 20 T2802 4509A-DECT-01/02 T2802 Figure 4. 3-Wire Bus Protocol Timing Diagram DATA CLOCK ENABLE TPER TL TS TC TH TEC TT Description Clock period Set time data to clock Hold time data to clock Clock pulse width Set time enable to clock Hold time enable to data Time between two protocols Symbol TPER TS TH TC TL TEC TT Minimum Value 125 60 60 125 200 0 250 Unit ns ns ns ns ns ns ns Figure 5. TX DATA Timing RefCLK TX_DATA TS TH Set-up time TX DATA Hold time TX DATA TS TH > 8 ns > 8 ns When using REFCLK = 10.368 MHz, TS and TH must be considered for falling and rising edge of REFCLK Absolute Maximum Ratings All voltages refer to GND Parameters Supply voltage regulator Supply voltage Logic input voltage Junction temperature Storage temperature Pin 10 Pins 7, 12, 14, 33 and 42 Pins 1, 2, 3, 38, 39, 44, 45, 46, 47 and 48 Symbol VS_REG VS VIN Tjmax Tstg -40 Min. 3.2 3.0 - 0.3 Max. 4.7 4.7 VS 150 150 Unit V V V C C 21 4509A-DECT-01/02 Thermal Resistance Parameters Junction ambient Symbol RthJA Value 25 Unit K/W Operating Range Parameters Supply voltage regulator Supply voltage Ambient temperature Pin 10 Pins 7, 12, 14, 33, 42 Symbol VS_REG VS Tamb Min. 3.2 2.9 -25 Typ. 3.6 3.0 Max. 4.6 4.6 +85 Unit V V C Electrical Characteristics Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25C Parameters IR mixer (Pins 29, 30, 40 and 41) Input impedance Input matching Image rejection ratio DSB noise figure Conversion gain Input intercept point IF amplifier (Pins 26, 27, 34 and 35) Input impedance Lower cut-off frequency Upper cut-off frequency Power gain Bandwidth of external tank circuit Noise figure RSSI (Pins 25, 34 and 35) RSSI sensitivity RSSI compression RSSI dynamic range RSSI resolution RSSI rise time RSSI fall time Quiescent output current Slope of the RSSI has to be steady Pin = 30 to 100 dBV, Pin 25 Pin = 100 to 30 dBV, Pin 25 at Pin < 20 dBV at IF_IN1, IF_IN2, Pin 25 at IF_IN1,2; Pins 34 and 35 at IF_IN1,2; Pins 34 and 35 Pmin Pmax DR Acc tr tf Iout 20 100 80 2 1 1 30 dBV dBV dB dB s s A Pins 26 and 27 Pins 34 and 35 Zin fl3dB fu3dB Gp BW3dB NF 200 90 130 85 10 9 400 MHz MHz dB MHz dB Pins 29 and 30 Pins 29 and 30 Pins 40 and 41 Pins 40 and 41 Rload = 200 Pins 40 and 41 Zin VSWRin IRR NFDSB= NFSSB Gconv IIP3 50 <2:1 20 10 11 -7 dB dB dB dBm Test Conditions/Pins Symbol Min. Typ. Max. Unit 22 T2802 4509A-DECT-01/02 T2802 Electrical Characteristics Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25C Parameters Maximum output current Test Conditions/Pins at Pin = 100 dBV at IF_IN1, IF_IN2, Pin 25 Symbol Iout Min. Typ. 150 Max. Unit A FM demodulator, BB-filter (Pins 19, 20, 23 and 24) Co-channel rejection ratio Sensitivity at Pin = -75 dBm at IR-mixer input Quality factor of external tank circuit approximately 20, fres = FIF/2, Pin 24 Nominal deviation of signal 288 kHz, Pin 24 Pin 23: C = 68 pF Pin 24 Pin 21 (see bus protocol E6 to E10) CCRR S 10 0.5 dB V/MHz Amplitude of recovered signal Corner frequency Output voltage DC range Output impedance DEMOD_DAC range VCOs Frequency range Tuning gain Frequency control voltage range VCO_DAC range PLL Scaling factor prescaler Scaling factor main counter Scaling factor swallow counter External reference input frequency A fc VoutDC Zout DfIFcenter fvco fvco Gtune Vtune fvco,DAC SPSC SMC SSC 0 2400 2289 1 450 680 VS-1 1.5 5 mVpp kHz V k % TX-VCO, D12 (VS)=1 RX-VCO, D12 (VS)=0 2500 2389 70 MHz MHz MHz/V Pin 17 (see bus protocol D3 ... D6) 0.4 5 2.8 V % 32 / 33 40 - 47 31 10.368 13.824 20.736 27.648 50 3/4/6/8 250 MHz MHz MHz MHz mVRMS AC coupled sinewave, Pin 4 fREF_CLK External reference input voltage Scaling factor reference counter Charge pump (Pin 13) Output current Output current Current scaling Leakage current AC coupled sinewave, Pin 4 VREF_CLK SRC VCP = VVS_CP / 2, I_CPSW = `1', Pin 48 VCP = VVS_CP / 2, I_CPSW = `0', Pin 48 ICP = ICP_nom + CPCS x ICP_step (see bus protocol D1 ... D2) ICP_nom ICP_nom ICP_step IL 5.5 1 0.2 100 mA mA mA pA Gaussian transmit filter (Gaussian shape B x T = 0.5) Tx data filter clock Frequency deviation 6 taps in filter fTXFCLK GFFM_nom 6.912 400 MHz kHz 23 4509A-DECT-01/02 Electrical Characteristics Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25C Parameters Frequency deviation scaling Modulation compensation circuit Oversampling Digital sum variation Current scaling factor TX driver (Pin 32) Maximum output power Minimum output power RF leakage Output impedance Ramp generator (Pins 36 and 37) Minimum output voltage Maximum output voltage Rise time Fall time Pin 36 and 37 (see bus protocol E6 - E10) Cramp = 270 pF at Pin 37 Cramp = 270 pF at Pin 37 locked = `1', unlocked = `0' test modes (see bus protocol E0 ... E2) VOH = 4.6 V IOL = 0.5 mA VSREG = 3 V, Pin 8 VPin10 = VDC + 0.1 Vpp fPin10 = 0.1 to 10 kHz CPin8 = 100 nF VSVCO = 3 V, Pin 15 Vmin Vmax tr tf 1.1 5 5 0.7 1.8 V V s s (see bus protocol E3 ... E5) @ L = 5.6 nH, Pin 32 (see bus protocol E11 - E12) @ L = 5.6 nH, Pin 32 (see bus protocol E11 - E12) In RX mode @ L = 5.6 pF, 2.5 GHz, Pin 32 OVS DSV MCCS 60 6 85 130 % Test Conditions/Pins GFFM = GFFM_nom GFCS (see bus protocol D7 ... D9) x Symbol GFCS Min. 60 Typ. Max. 130 Unit % PTX PTX Pleak ZOUT 3 -21 -47 13+j40 dBm dBm dBm Lock detect and test mode output (Pin 5) Lock detect output, test mode output LD Leakage current Saturation voltage IL VSL VREG SVR 2.9 3.0 TBD 5 0.4 A V Auxiliary regulator (Pins 8, 9 and 10) Output voltage Supply voltage rejection 3.1 V dB VCO regulator (Pins 14, 15 and 12) Output voltage 3-wire bus Clock fClock 6.912 MHz VREG_VCO 2.6 2.7 2.8 V Logic input levels (CLOCK, DATA, ENABLE, RX_ON, TX_ON, PU_VCO, TX_DATA, DATA_HOLD) (Pins 1, 2, 3, 38, 39, 44, 47 and 48) High input level Low input level High input current Low input current = `1' = `0' = `1' = `0' ViH ViL IiH IiL -5 -5 1.5 0.5 5 5 V V A A 24 T2802 4509A-DECT-01/02 T2802 Electrical Characteristics Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25C Parameters Standby control (Pins 6, 45 and 46) Power up PU_REG = `1` PU_RX/TX = `1` PU_PLL = `1` High input level Standby PU_REG = `0` PU_RX/TX = `0` PU_PLL = `0` Low input level Power up PU_REG = `1` PU_RX/TX = `1` PU_PLL = `1` High input current Standby PU_xxxx = `0' Low input current Settling time VS = 0 active operation Settling time standby active operation Settling time active operation standby Pin 6 Pin 45 Pin 46 VPU_REG VPU_RX/TX VPU_PLL Test Conditions/Pins Symbol Min. Typ. Max. Unit 2.0 V Pin 6 Pin 45 Pin 46 VPU_REG,OFF VPU_RX/TX,OFF VPU_PLL,OFF 0.7 V VPU = 3 V, Pin 6 VPU = 4.6 V, Pin 45 VPU = 3 V, Pin 46 VPU = 4.6 V VPU = 0 V, Pin 6 VPU = 0.5 V, Pins 45, 46 Switched from VS = 0 to VS = 3V Switched from PU = `0' to PU = `1' Switched from PU = `1' to standby IPU_REG IPU_RX/TX IPU_PLL 20 60 100 200 30 80 125 300 40 100 150 400 0.1 1 A A A A A A s s s IPU,OFF tsoa tssa tsas IS IS IS IS IS IS ICP < 10 < 10 <2 Power supply (Pins 7, 10, 12, 14, 33 and 42) Total supply current RX RSSI only TX TX (MCC, GF active) Standby current, mode 1 mode 2 Supply current CP PU_RX/TX = GND PU = GND, ATA_HOLD = VS VVS_CP = 3 V, PLL in lock condition, Pin 13 85 82 54 58 1 50 1 10 100 mA mA mA mA A A A 25 4509A-DECT-01/02 Figure 6. Typical Application Circuit RAMP_OUT 47 pF TX_OUT RF_IN 180 nH 100 nH SAW Filter TFS 112B 47pF 18 pF 27 pF 68 pF GND3 31 RAMP_OUT 36 TX_OUT 32 RF_IN2 30 RF_IN1 29 IF_IN2 35 IF_IN1 34 VS_IF 33 GND2 28 RSSI 25 RSSI 27 pF 56 pF 37 RAMP_SET RX_ON TX_ON 38 RX_ON 39 TX_ON IF_TANK2 27 IF_TANK1 26 150 nH BB_OUT 24 BB_CF 23 REG_DEC 22 DAC_DEC 21 BB_OUT 68 pF 2.2 nF 100 pF tbd tbd 40 MIXER_OUT1 41 MIXER_OUT2 42 VS_MIXER 43 GND_PLL PU_VCO PU_RX/TX PU_PLL TX_DATA I_CPSW T2802 DEMOD_TANK2 20 DEMOD_TANK1 19 GND1 18 VTUNE 17 GND_VCO 16 VREG_VCO 15 44 PU_VCO 45 PU_RX/TX 46 PU_PLL 4 REF_CLOCK 22 nF 47 TX_DATA 3 ENABLE VS_VCO 14 9 REG_CTRL 11 GND_CP 6 PU_REG 10 VS_REG 7 VS_PLL 12 VS_CP 180 W 150 nF 48 I_CPSW 1 CLOCK 2 DATA CP 13 8 VREG 5 LD 56 pF 470 nF CLOCK DATA ENABLE REF_CLK LD 220 pF PU_REG 4.7 nF VCC BC808 or similar tantal tantal 26 T2802 4509A-DECT-01/02 T2802 Ordering Information Extended Type Number T2802-PLH Package HP-VFQFP-N48 Remarks Taped and reeled Package Information 27 4509A-DECT-01/02 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 RF/Automotive Atmel Heilbronn Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Microcontrollers Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 Atmel Nantes La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 ASIC/ASSP/Smart Cards Atmel Rousset Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Atmel Smart Card ICs Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Atmel (R) is the registered trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper. 4509A-DECT-01/02 xM |
Price & Availability of T2802NBSP
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |